1. Field of the Invention
The present invention relates to buses for transferring data in digital systems. More specifically, the present invention relates to a method and an apparatus for enhancing the timing margins and the reliability of digital system buses.
2. Related Art
Many computer buses now operate at giga-hertz rates which presents challenges to the system designers to maintain high reliability in the face of smaller timing margins.
The timing margins on these high-speed buses are affected by a number of small, but important effects. Included in these small effects are temperature effects, transmission line effects, first-pulse distortion effects, and timing jitter caused by pattern sensitive crosstalk effects.
The temperatures of driver and receiver transistors on a digital bus change depending on the power being dissipated within the transistors. The power being dissipated, in turn, depends on the data transitions on the bus. During idle times on the bus, driver and receiver transistors are not switching, which reduces the power being dissipated by the transistors. This can cause the temperatures of the driver and receiver transistors to change from their nominal values, thereby changing the characteristics of the bus when data transmissions resume. When data transmissions resume, it can take many data cycles for the temperatures to stabilize, which causes temperature induced effects on the timing margins.
Transmission line effects are caused by slight mismatches in impedance between the devices on the digital system bus and the terminations of the signal lines on the bus. As bus temperatures change, the impedance of the active devices changes. This mismatch of impedance causes signal reflections on the signal lines. These reflected signals appear as noise relative to the signals and can adversely affect the timing margins.
First pulse distortion effects follow from the digital system bus being held at a constant state during idle periods. After an idle period, the first pulse to be transmitted over the bus is distorted by a combination of mechanisms. Included in these mechanisms are changes in power supply voltages, and changes in device temperatures.
What is needed is a method and an apparatus for alleviating the detrimental effects listed above, thereby allowing reduced timing margins and greater reliability of the digital system bus.